IP3 2023 – Semiconductor Devices (LOT 13803)

This lot is generally related to a logic semiconductor device for performing memorization operation and inference with low power so that large data processing speed can be achieved. Disclosed is a semiconductor device consisting of stacked transistors having a semiconductor column with a first conductive region of a first conductivity type, a second conductive region of a second conductivity type. The device has an intrinsic region between the first conductive region and the second conductive region and a barrier region between the intrinsic region and the second conductive region. Also disclosed is a gate electrode covering the intrinsic region and a gate insulating layer disposed between the gate electrode and the intrinsic region. The stacked transistors have a first transistor of n-type disposed at a lower portion and a second transistor of p-type disposed above the first transistor. The technology may be implemented in logic semiconductor devices, CMOS based neuromorphic circuits, etc.